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| publication release date: september 2005 - 1 - revision a.2 w681360 3v single-channel 13-bit linear voice-band codec data sheet
w681360 publication release date: september 2005 - 2 - revision a2 1. general description the w681360 is a general-purpose single channel 13?bit linear pcm codec with 2s complement data format. it operates from a single +3v power su pply and is available in 20-pin sog(sop), ssop and tssop package options. the primary function of t he device is the digitization and reconstruction of voice signals, including the band limiting and smoothing required for pcm systems. the w681360 performance is specified over the i ndustrial temperature range of ?40 c to +85 c. the w681360 includes an on-chip precision voltage reference. the analog section is fully differential, reducing noise and improving the power supply rejection ratio. the v ag reference pin allows for decoupling of the internal circuitry that generates the reference voltage to the v ss power supply ground, minimizing clock noise on the analog circuitry when external analog signals are referenced to v ss . the data transfer protocol supports both long-frame and short-frame, synchronous and asynchronous communications for pcm applications. the w681360 accepts eight master clock rates between 256khz and 4.800mhz, and an on-chip pre-scaler auto matically determines the division ratio for the required internal clock. an additional on-chip power amplifier is capable of driving 300 loads differentially up to a level of 3.544v peak-to-peak. for fast evaluation a development kit (w681360dk) is available. for fast prototyping purposes a low-cost eval uation board (w681360es) is also available. 2. features ? single +3v power supply (2.7v to 5.25v) ? typical power dissipation: 9.8mw standby power dissipation: 3w power-down dissipation: 0.09w ? fully-differential analog circuit design for low noise ? 13-bit linear a/d & d/a conversions with 2s complement data format ? codec a/d and d/a filtering compliant with itu g.712 ? eight master clock rates of 256khz to 4.800 mhz ? 256khz ? 4.8mhz bit clock rates on the serial pcm port ? on-chip precision reference of 0.886 v for a -5 dbm tlp at 600 (436mv rms ) ? ? programmable receive gain: 0 to ?21db in 3db steps ? industrial temp. range (?40 c to +85 c) ? 20-pin sog (sop), ssop and tssop as well as a qfn-32l package ? pb-free / rohs package options available applications ? voip, voice over networks equipment ? digital telephone and communication systems ? wireless voice devices ? dect/digital cordless phones ? broadband access equipment ? bluetooth headsets ? fiber-to-curb equipment ? enterprise phones ? digital voice recorders w681360 publication release date: september 2005 - 3 - revision a.2 3. block diagram 256 khz 512 khz 1536 khz 1544 khz 2048 khz 2560 khz 4096 khz 4800 khz mclk 256 khz 8 khz pre-scaler v dd v ss power conditioning voltage reference v ag pui g.712 codec pao+ pao- pai ro- ao ai+ ai- hb transmit pcm interface receive pcm interface fst bclkt pcmt fsr bclkr pcmr v agref 256 khz 512 khz 1536 khz 1544 khz 2048 khz 2560 khz 4096 khz 4800 khz mclk 256 khz 8 khz pre-scaler v dd v ss power conditioning voltage reference v ag pui g.712 codec pao+ pao- pai ro- ao ai+ ai- hb transmit pcm interface receive pcm interface fst bclkt pcmt fsr bclkr pcmr v agref w681360 publication release date: september 2005 - 4 - revision a.2 4. table of contents 1. general description .................................................................................................................. 2 2. features ......................................................................................................................................... 2 3. block diagram ............................................................................................................................... 3 4. table of contents ...................................................................................................................... 4 5. pin configuration ....................................................................................................................... 6 6. pin description ............................................................................................................................. 7 7. functional description ............................................................................................................ 8 7.1. transmit path ............................................................................................................................... .8 7.1.1 input operational amplifier gain ............................................................................................. 9 7.2. receive path ............................................................................................................................... 10 7.2.1. receive gain adjust mode ................................................................................................... 11 7.3. power management .................................................................................................................... 11 7.3.1. analog and digital supply .................................................................................................... 11 7.3.2. analog ground reference bypass ...................................................................................... 11 7.3.3. analog ground reference voltage output .......................................................................... 11 7.4. pcm interface ............................................................................................................................. 12 7.4.1. long frame sync ................................................................................................................. 12 7.4.2. short frame sync ................................................................................................................ 12 7.4.3. special 16-bit receive modes .............................................................................................. 13 7.4.3.1. sign-extended mode timing ............................................................................................. 13 7.4.3.2. receive gain adjust mode timing .................................................................................... 13 7.4.4. system timing ..................................................................................................................... 14 7.5. on-chip power amplifier ............................................................................................................ 14 8. timing diagrams .......................................................................................................................... 15 9. absolute maximum ratings .................................................................................................... 20 9.1. absolute maximum ratings ........................................................................................................ 20 9.2. operating conditions .................................................................................................................. 20 10. electrical characteristics ............................................................................................... 21 10.1. general parameters ................................................................................................................. 21 10.2. analog signal level and gain parameters ............................................................................... 22 10.3. analog distortion and noise parameters ................................................................................. 23 10.4. analog input and output amplifier parameters ........................................................................ 24 10.5. digital i/o ............................................................................................................................... ... 26 10.5.1. pcm codes for zero and full scale .................................................................................. 26 10.5.2. pcm codes for 1khz digital milliwatt ................................................................................ 26 11. typical application circuit ................................................................................................. 27 12. package drawing and dimensions .................................................................................... 28 12.1. 20l sog (sop)-300mil ............................................................................................................ 28 12.2. 20l ssop-209 mil .................................................................................................................... 29 12.3. 20l tssop - 4.4x6.5mm ......................................................................................................... 30 12.3. qfn-32l ............................................................................................................................... .... 31 w681360 publication release date: september 2005 - 5 - revision a.2 13. ordering information ........................................................................................................... 32 14. version history ....................................................................................................................... 33 w681360 publication release date: september 2005 - 6 - revision a.2 5. pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 272829 30 31 32 ro- pai pao- pao+ nc v dd fsr pcmr bclkr nc ai- ao nc hb v ss fst nc pcmt nc nc pui mclk nc nc bclkt nc nc v ref v ag nc nc ai+ qfn-32l 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 272829 30 31 32 ro- pai pao- pao+ nc v dd fsr pcmr bclkr nc ai- ao nc hb v ss fst nc pcmt nc ai- ao nc hb v ss fst nc pcmt nc nc pui mclk nc nc bclkt nc nc pui mclk nc nc bclkt nc nc v ref v ag nc nc ai+ qfn-32l 20 19 18 17 16 15 14 13 12 11 w681360 single channel codec 1 2 3 4 5 6 7 8 9 10 sog, ssop,tssop v ref ro- pai pao- pao+ v dd fsr pcmr bclkr pui v ag ai+ ai- ao hb v ss fst pcmt bclkt mc lk 20 19 18 17 16 15 14 13 12 11 w681360 single channel codec 1 2 3 4 5 6 7 8 9 10 sog, ssop,tssop v ref ro- pai pao- pao+ v dd fsr pcmr bclkr pui v ag ai+ ai- ao hb v ss fst pcmt bclkt mc lk w681360 publication release date: september 2005 - 7 - revision a.2 6. pin description pin no. pin name non- qfn qfn functionality v ref 1 30 this pin is used to bypass the on?chip v dd /2 voltage reference for the v ag output pin. this pin should be bypassed to v ss with a 0.1 f ceramic capacitor using short, low inductance traces. the v ref pin is only used for generating the reference voltage for the v ag pin. nothing is to be connected to this pin except the bypass capacitor. ro- 2 1 inverting output of the receive smoothing filter. this pin can typically drive a 2k load to 0.886v peak referenced to analog ground. pai 3 2 inverting input to the power amplifier. the non-inverting input is tied internally to v ag voltage. pao- 4 3 inverting power amplifier output. the pao- and pao+ can drive a 300 load differentially to 1.772v peak . pao+ 5 5 non-inverting power amplifier output. the pao- and pao+ can drive a 300 load differentially to 1.772v peak . v dd 6 6 power supply. should be decoupled to v ss with a 0.1 f ceramic capacitor. fsr 7 7 8khz frame sync input for the pcm rece ive section. fsr can be asynchronous to fst in either long frame sync or short frame sync mode. pcmr 8 8 pcm input data receive pin. the data needs to be synchronous with the fsr and bclkr pins. bclkr 9 9 pcm receive bit clock input pin. can ac cept any bit clock frequency from 256 to 4800khz. when not clocked it can be used to sele ct the 16 sign-bit ex tended synchronous mode (bclkr=0) or the receive gain adjust synchronous mode (bclkr=1) pui 10 12 power up input signal. when this pin is tied to v dd , the part is powered up. when tied to v ss , the part is powered down. mclk 11 13 system master clock input. possibl e input frequencies are 256khz, 512khz, 1536khz, 1544khz, 2048khz, 2560khz, 4096khz & 4800khz . for performance reasons, it is recommended that mclk be synchronous and aligned to the fst signal. this is a requirement in the case of 256 and 512khz frequencies. bclkt 12 16 pcm transmit bit clock input pin. can accept any bit clock frequency from 256 to 4800khz. pcmt 13 17 pcm output data transmit pin. the out put data is synchronous with the fst and bclkt pins. fst 14 19 8khz transmit frame sync input. this pin synchronizes the transmit data bytes. v ss 15 20 this is the supply ground. this pin should be connected to 0v. hb 16 22 high-pass bypass. determines if the transmit high-pass filter is used (hb=?0?) or bypassed (hb=?1?). when the high pass is bypas sed the frequency response extends to dc. ao 17 23 analog output of the first gain stage in the transmit path. ai- 18 24 inverting input of the first gain stage in the transmit path. ai+ 19 26 non-inverting input of the fi rst gain stage in the transmit path. v ag 20 29 mid-supply analog ground pin, which supplies a v dd /2 volt reference voltage for all- analog signal processing. this pin should be decoupled to v ss with a 0.01 f capacitor. this pin becomes high impedance when the chip is powered down. w681360 publication release date: september 2005 - 8 - revision a.2 7. functional description w681360 is a single-rail, single channel pcm codec for voiceband applications. the codec complies with the specifications of the itu-t g.712 recommendation. the codec block diagram in section 3 illustrates the main components of the w681360. the chip consists of a pcm interface, which can process lo ng and short frame sync form ats. the pre-scaler of the chip provides the internal clock signals and synchronizes the codec sample rate with the external frame sync frequency. the power conditi oning block provides the internal power supply for the digital and the analog section, while the vo ltage reference block provides a precision analog ground voltage for the analog signal processing. the calibration level for both the analog to di gital converter (adc) and the digital to analog converter (dac) is referenced to -law with the same bit voltage weighing about the zero crossing, resulting in the 0dbm0 calibration level 3.2db below the peak sinusoidal level before clipping, based on the reference voltage of 0.886v the calib ration level is 0.436 vrms or ?5dbm at 600 ? . 13 high pass bypass 13 bit linear dac smoothing filter b f c = 3400 hz smoothing filter a buffer1 av=1 data receive ro- 13 ai- ao - + anti-aliasing filter b f c = 3400 hz anti-aliasing filter a f c = 200 hz high pass filter 13 bit linear adc data transmit ai+ pai pao+ + - pao- - + vag 13 high pass bypass 13 bit linear dac smoothing filter b f c = 3400 hz smoothing filter a buffer1 av=1 data receive ro- 13 ai-ai- ao - + anti-aliasing filter b f c = 3400 hz anti-aliasing filter a f c = 200 hz high pass filter 13 bit linear adc data transmit ai+ai+ pai pao+ + - pao- - + vag figure 7.1: the w681360 signal path 7.1. transmit path the first stage of the a-to-d path of t he codec is an analog input operational amplifier with externally configurable gain settings. a differential analog input may be applied to the inputs ai+ and ai -. alternately the input amplifier may be powered down and a single-ended input signal can be appl ied to either the ao pin or the ai- pin. the input amplifier c an be powered down by connecting the ai+ pin to either v dd or v ss which also determines whether ao or ai+ is selected as input according to w681360 publication release date: september 2005 - 9 - revision a.2 table 7.1. when the input operational amplifier is powered down the ao pin becomes high input impedance. table 7.1: input amplifier modes of operation ai+ (pin 19) input amplifier input v dd powered down ao (pin 17) 1.2 to v dd -1.2 powered up ai+, ai- (pins 19, 18) v ss powered down ai- (pin 18) when the input amplifier is powered down, the input signal at ao or ai- should be referenced to the analog ground voltage v ag . the output of the input operational amplifier is first fed through a low-pass filter to prevent aliasing at the switched capacitor 3.4khz low pass filter. subsequently the 3.4khz switched capacitor low pass filter bandlimits the input signals well below 4khz . signals above 4khz would be aliased at the sampling rate of 8khz. a high pass filter with a 200hz cut-off frequency prevents dc coupling. all filters are designed according to the g.712 itu-t s pecification. the high-pass filter may be bypassed depending on the logic level on the hb pin. if the high pass is removed the frequency response of the device extends down to dc. after filtering the signal is digitized as a 13-bit linear pcm code and fed to the pcm interface for serial transmission at the sample rate supplie d by the external frame sync fst. 7.1.1 input operational amplifier gain the gain of the input operational amplifier can be adjusted using external resistors. for single-ended input operation the gain is given by a simple resistive ratio. figure 7.2: input operational am plifier gain ? single-ended input gin = ro/ri vin vag - + ai+ ai- ao ri ro for differential input operation the external resistor network is more complex but the gain is expressed in the same way. of course, a differential input also has an inherent 6db advantage over a corresponding single-ended input. w681360 publication release date: september 2005 - 10 - revision a.2 ai+ ai- vin+ vin- ao ri vag - + ri ro gin = ro/ri ro figure 7.3: input operational am plifier gain ? differential input the gain of the operational amplifier will be typically be set to 30db for microphone interface circuits. however the gain may be used for more than 30db but this will require a compact layout with minimal trace lengths and good isolation from noise sources. it is also recommended that the layout be as symmetrical as possible as imbalances work agains t the noise canceling advantages of the differential design. 7.2. receive path the 13-bit digital input samples for the d-to-a pat h are serially shifted in by the pcm interface and converted to parallel data bits. during every cycle of the frame sync fsr, the parallel data bits are fed through the 13-bit linear dac and converted to anal og samples. the analog samples are filtered by a low-pass smoothing filter with a 3.4khz cut-off fr equency, according to the itu-t g.712 specification. a sin(x)/x compensation is integrated with the low pa ss smoothing filter. the output of this filter is buffered to provide the receive output signal ro-. the output may be also be attenuated when the device is in the receive path adjust mode. if the device is operated half?channel with the fst pin clocking and fsr pin held low, the receive filter input will be connected to the v ag voltage. this minimizes transients at the ro? pin when full?chan nel operation is resumed by clocking the fsr pin. the ro- output can be externally connected to the pai pin to provide a differential output with high driving capability at the pao+ and pao- pins. by using external resistors various gain settings of this output amplifier can be achieved. if the transmit power amplifier is not in use, it can be powered down by connecting pai to v dd . the bias voltage and signal reference of the pao+ & pao? outputs is the v ag pin. the v ag pin cannot source or sink as much current as these pins, and therefore low impedance loads must be placed between pao+ and pao?. the pao+ and pao? differential drivers are also capable of driving a 100 ? resistive load or a 100nf piezoelectric transducer in series with a 20 ? resister with a small increase in distortion. th ese drivers may be used to drive resistive loads of 32? when the gain of pao? is set to 1/4 or less. w681360 publication release date: september 2005 - 11 - revision a.2 7.2.1. receive gain adjust mode the w681360 can be put in the receive path adjus t mode by applying a logic ?1? to the bclkr pin while all other clocks are clocked normally. the dev ice is then in a position to read 16-bits of data, with three additional coefficient bits an addend to th e 13-bit digital voice data. these three coefficients are used to program a receive path attenuation, thereby allowing the receive signal to be attenuated according to the values in the following table. if the feature is not used the default value is 0db. table 7.2: attenuation coefficient relati onship in receive gain adjust mode coefficient attenuation (db) 000 0 001 3 010 6 011 9 100 12 101 15 110 18 111 21 7.3. p ower m anagement 7.3.1. analog and digital supply the power supply for the analog and digital parts of the w681360 must be 2.7v to 5.25v. this supply voltage is connected to the v dd pin. the v dd pin needs to be decoupled to ground through a 0.1 f ceramic capacitor. 7.3.2. analog ground reference bypass the system has an internal precision voltage reference which generates the v dd /2 mid-supply analog ground voltage. this voltage needs to be decoupled to v ss at the v ref pin through a 0.1 f ceramic capacitor. 7.3.3. analog ground reference voltage output the analog ground reference voltage is avail able for external reference at the v ag pin. this voltage needs to be decoupled to v ss through a 0.01 f ceramic capacitor. the analog ground reference voltage is generated from the voltage on the v ref pin and is also used for the internal signal processing. w681360 publication release date: september 2005 - 12 - revision a.2 7.4. pcm i nterface the pcm interface is controlled by pins bclkr, fsr, bclkt & fst. the input data is received through the pcmr pin and the output data is transmitted through the pcmt pin. the long frame sync or short frame sync interface mode can be selected by connecting the bclkr or bclkt pin to a 256khz to 4.800 mhz clock and co nnecting the fsr or fst pin to the 8khz frame sync. the device synchronizes the data word fo r the pcm interface and the codec sample rate on the positive edge of the frame sync signal. long fram e sync is recognized when the fst pin is held high for two consecutive falling edges of the bit-cl ock at the bclkt pin. short frame sync mode is recognized when the frame sync si gnal at pin fst is high for one and only one falling edge of the bit-clock at the bclkt pin. 7.4.1. long frame sync the device recognizes a long frame sync when the fs t pin is held high for two consecutive falling edges of the bit-clock at the bclkt pin. the length of the frame sync pulse can vary from frame to frame, as long as the positive frame sync edge occurs every 125 sec. during data transmission in the long frame sync mode, the transmit data pin pc mt will become low impedance when the frame sync signal fst is high or when the 13-bit dat a word is being transmitted. the transmit data pin pcmt will become high impedance when the frame sy nc signal fst becomes low while the data is transmitted or when half of the lsb is transmitted. the internal decision logic will determine whether the next frame sync is a long or a short frame sync, based on the previous frame sync pulse. to avoid bus collisions, the pcmt pin will be high impedance fo r two frame sync cycles after every power down state. long frame sync mode is illustrated below. more detailed timing information can be found in the interface timing section. long frame sync (transmit and receive have individual clocking) fst (fsr) pcmt 7 654321 bclkt (bclkr) 1211 10 98 13 pcmr 7 654321 1211 10 98 13 don't care don't care figure 7.4: long frame sync pcm mode 7.4.2. short frame sync the w681360 operates in the short frame sync mode when the frame sync signal at pin fst is high for one and only one falling edge of the bit-clock at the bclkt pin. on the following rising edge of the bit-clock, the w681360 starts clocking ou t the data on the pcmt pin, which will also change from high to low impedance state. the data tran smit pin pcmt will go ba ck to the high impedance state halfway through the lsb. the short frame sy nc operation of the w681360 is based on a 13-bit data word. when receiving data on the pcmr pin, the data is clocked in on the first falling edge after the falling edge that coincides with the frame sync signal. the inter nal decision logic will determine whether the next frame sync is a long or a short frame sync, based on the previous frame sync pulse. to avoid bus collisions, the pcmt pin will be high impedance for two frame sync cycles after every power down state. short frame sync mode is illust rated below. more detailed timing information can be found in the interface timing section. w681360 publication release date: september 2005 - 13 - revision a.2 short frame sync (transmit and receive have individual clocking) fst (fsr) pcmt 7 654321 bclkt (bclkr) 1211 10 98 13 pcmr 7 654321 1211 10 98 13 don't care don't care figure 7.5: short frame sync pcm mode 7.4.3. special 16-bit receive modes 7.4.3.1. sign-extended mode timing the sign-bit extended mode is entered by applying a logi c ?0? to the bclkr pin while all other clocks are clocked normally. in standard 13-bit mode the first bit is the sign bit. in this mode the device transmits and receives 16-bit data where the sign bi t is extended to the first four data bits. the pcm timing for this mode is illustrated below. sign-extended (bclkr=0) transmit and receive both use bclkt, and the first four data bits are the sign bit. fst may occur at a different time than fsr fst (fsr) short or long frame sync pcmt 7 654321 bclkt (bclkr) 1211 10 98 13 pcmr 7 654321 1211 10 98 13 don't care don't care 15 14 16 15 14 16 don't care figure 7.6: sign extended mode 7.4.3.2. receive gain adjust mode timing the receive path adjust mode is entered by applyi ng a logic ?1? to the bclkr pin while all other clocks are clocked normally. in this mode the device receives 16-bit data where the last three bits are coefficients to program the receive gain adjust attenuation described above. the pcm timing for this mode is illustrated below. w681360 publication release date: september 2005 - 14 - revision a.2 receive gain adjust (bclkr=1) transmit and receive both use bclkt. fst may occur at a different time than fsr. bits 14, 15, and 16, clocked into pcmr, are used for attenuation control for the receive analog output. fst (fsr) short or long frame sync pcmt 7 654321 bclkt (bclkr) 121110 98 pcmr 7 654321 121110 98 13 don't care don't care 13 1514 16 don't care figure 7.7: receive gain adjust timing mode 7.4.4. system timing the system can work at 256khz, 512khz, 1536 khz, 1544khz, 2048khz, 2560khz, 4096khz & 4800khz master clock rates. the system clock is supplied through the master clock input mclk and can be derived from the bit-clock if desired. an in ternal pre-scaler is used to generate a fixed 256khz and 8khz sample clock for the internal codec. the pre-scaler measures the master clock frequency versus the frame sync frequency and sets the division ratio accordingly. if both frame syncs are low for the entire frame sync period while the mclk and bclk pin clock signals are still present, the w681360 will enter the low power standby mode. anot her way to power down is to set the pui pin to low. when the system needs to be powered up again, the pui pin needs to be set to high and the transmit frame sync pulse needs to be present. it will take two transmit frame sync cycles before the pin pcmt becomes low impedance. 7.5. o n -c hip p ower a mplifier the on-chip power amplifier is typically used to drive an external loudspeaker. the inverting input to the power amplifier is available at pin pai. the non-inverting input is tied internally to v ag. the inverting output pao? is used to provide a feedback si gnal to the pai pin to set the gain of the power amplifier outputs (pao+ and pao-). these push?pull outputs are capable of driving a 300 ? load to 1.772 v peak . connecting pai to v dd will power down the power driver amplifiers and the pao+ and pao? outputs will be high impedance. w681360 publication release date: september 2005 - 15 - revision a.2 8. timing diagrams t ftrh t ftrs t ftfh t fdtd t fdtd t bdtd t bckh t bckl t bck t hid t hid t rise t fall t mck t mckh t ftrhm t ftrsm t mckl t fs t fsl t frrh t frrs t frfh t bckh t bckl t drs t drh mclk bclkt fst pcmt bclkr (bclkt) fsr pcmr t bck msb lsb msb lsb figure 8.1: long frame sync pcm timing note: the data is clocked out on the rising edge of bclk. the data is clocked in on the falling edge of bclk. w681360 publication release date: september 2005 - 16 - revision a.2 table 8.1: long frame sync pcm timing parameters symbol description min typ max unit 1/t fs fst, fsr frequenc y --- 8 --- khz t fsl fst / fsr minimum low width 1 t bck sec 1/t bck bclkt, bclkr frequency 1 256 --- 4800 khz t bckh bclkt, bclkr high pulse width 50 --- --- ns t bckl bclkt, bclkr low pulse width 50 --- --- ns t ftrh bclkt falling edge to fst rising edge hold time 20 --- --- ns t ftrs fst rising edge to bclkt falling edge setup time 80 --- --- ns t ftfh bclkt falling edge to fst falling edge hold time 50 --- --- ns t fdtd the later of bclkt rising edge, or fst rising edge to first valid pcmt bit delay time --- --- 60 ns t bdtd bclkt rising edge to valid pcmt delay time --- --- 60 ns t hid delay time from the later of fst falling edge, or bclkt falling edge of last pcmt bit to pcmt output high impedance 10 --- 60 ns t frrh bclkr falling edge to fsr rising edge hold time 20 --- --- ns t frrs fsr rising edge to bclkr falling edge setup time 80 --- --- ns t frfh bclkr falling edge to fsr falling edge hold time 50 --- --- ns t drs valid pcmr to bclkr falling edge setup time 1 --- --- ns t drh pcmr hold time from bclkr falling edge 50 --- --- ns 1 t fsl must be at least t bck w681360 publication release date: september 2005 - 17 - revision a.2 figure 8.2: short frame sync pcm timing t ftrh t ftrs t ftfh t bdtd t bckh t bckl t bck t hid t rise t fall t mck t mckh t ftrhm t ftrsm t mckl t fs t frrh t frrs t frfh t bckh t bckl t drs t drh mclk bclkt fst pcmt bclkr (bclkt) fsr pcmr t bdtd t ftfs t bck t frfs msb lsb msb lsb w681360 publication release date: september 2005 - 18 - revision a.2 table 8.2: short frame sy nc pcm timing parameters symbol description min typ max unit 1/t fs fst, fsr frequency --- 8 --- khz 1/t bck bclkt, bclkr frequency 256 --- 4800 khz t bckh bclkt, bclkr high pulse width 50 --- --- ns t bckl bclkt, bclkr low pulse width 50 --- --- ns t ftrh bclkt falling edge to fst rising edge hold time 20 --- --- ns t ftrs fst rising edge to bclkt falling edge setup time 80 --- --- ns t ftfh bclkt falling edge to fst falling edge hold time 50 --- --- ns t ftfs fst falling edge to bclkt falling edge setup time 50 --- --- ns t bdtd bclkt rising edge to valid pcmt delay time 10 --- 60 ns t hid delay time from bclkt falling edge at last pcmt bit (lsb) to pcmt output high impedance 10 --- 60 ns t frrh bclkr falling edge to fsr rising edge hold time 20 --- --- ns t frrs fsr rising edge to bclkr falling edge setup time 80 --- --- ns t frfh bclkr falling edge to fsr falling edge hold time 50 --- --- ns t frfs fsr falling edge to bclkr falling edge setup time 50 --- --- ns t drs valid pcmr to bclkr falling edge setup time 1 --- --- ns t drh pcmr hold time from bclkr falling edge 50 --- --- ns w681360 publication release date: september 2005 - 19 - revision a.2 table 8.3: general pcm timing parameters symbol description min typ max unit 1/t mck master clock frequency --- 256 512 1536 1544 2048 2560 4096 4800 --- khz t mckh / t mck mclk duty cycle for 256khz operation 45% 55% t mckh minimum pulse width high for mclk(512khz or higher) 50 --- --- ns t mckl minimum pulse width low for mclk (512khz or higher) 50 --- --- ns t ftrhm mclk falling edge to fst rising edge hold time 50 --- --- ns t ftrsm fst rising edge to mclk falling edge setup time 50 --- --- ns t rise rise time for all digital signals --- --- 50 ns t fall fall time for all digital signals --- --- 50 ns w681360 publication release date: september 2005 - 20 - revision a.2 9. absolute maximum ratings 9.1. a bsolute m aximum r atings condition value junction temperature 150 0 c storage temperature range -65 0 c to +150 0 c voltage applied to any pin (v ss - 0.3v) to (v dd + 0.3v) voltage applied to any pin (input current limited to +/-20 ma) (v ss ? 1.0v) to (v dd + 1.0v) v dd - v ss -0.5v to +6v 1. stresses above those listed may cause permanent damage to the device. ex posure to the absolute maximum ratings may affect device reliability. functi onal operation is not implied at these conditions. 9.2. o perating c onditions condition value industrial operating temperature -40 0 c to +85 0 c supply voltage (v dd ) +2.7v to +5.25v ground voltage (v ss ) 0v note : exposure to conditions beyond those listed un der absolute maximum ratings may adversely affect the life and reliability of the device. w681360 publication release date: september 2005 - 21 - revision a.2 10. electrical characteristics 10.1. g eneral p arameters v dd =2.7v ? 3.6v; v ss =0v; t a =-40 c to +85 c; symbol parameters conditions min (2) typ (1) max (2) units v il input low voltage 0.6 v v ih input high voltage 2.2 v v ol pcmt output low voltage i ol = 1.6 ma 0.4 v v oh pcmt output high voltage i ol = -1.6 ma v dd ?0.5 v i dd v dd current (operating) - adc + dac no load 3.25 4.7 ma i sb v dd current (standby) fst&fsr =v ss ; pui=v dd (3) 1 100 a i pd v dd current (power down) pui= v ss (3) 0.03 10 a i il input leakage current v ss w681360 publication release date: september 2005 - 23 - revision a.2 10.3. a nalog d istortion and n oise p arameters v dd =2.7v to 3.6v; v ss =0v; t a =-40 c to +85 c; all analog signals referred to v ag ; 0dbm0 = 0.436 vrms = - 5dbm @ 600 ohm; fst =fsr = 8khz;mclk=bclk= 2.048 mhz transmit (a/d) receive (d/a) parameter sym. condition min. typ. max. min. typ. max. unit total distortion vs. level tone (1020hz, c- message weighted) d lt +3 dbm0 0 dbm0 -10 dbm0 -20 dbm0 -30 dbm0 -40 dbm0 -50 dbm0 -60 dbm0 45 50 51 50 41 32 22 12 55 60 60 54 44 34 24 14 --- --- --- --- --- --- --- --- 50 48 45 48 45 35 25 14 60 63 60 55 47 37 27 17 --- --- --- --- --- --- --- --- dbc spurious out-of- band at ro- (300hz to 3400hz @ 0dbm0) d spo 4600hz to 7600hz 7600hz to 8400hz 8400hz to 100000hz --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- -30 -40 -30 db crosstalk (1020hz @ 0dbm0) d xt --- --- -75 --- --- -75 db absolute group delay abs 1200hz (hb=0) --- --- 360 --- --- 240 sec group delay distortion (relative to group delay @ 1200hz) d 500hz 600hz 1000hz 2600hz 2800hz --- --- --- --- --- --- --- --- --- --- 750 380 130 130 750 --- --- --- --- --- --- --- --- --- --- 750 370 120 120 750 sec idle channel noise n idl c-message weighted psophometric weighted --- --- --- --- 18 -72 --- --- --- --- 12 -74 dbrnc0 dbm0p w681360 publication release date: september 2005 - 24 - revision a.2 10.4. a nalog i nput and o utput a mplifier p arameters v dd =2.7v to 3.6v; v ss =0v; t a =-40 c to +85 c; all analog signals referred to v ag ; parameter sym. condition min. typ. max. unit. ai input offset voltage v off,ai ai+, ai- --- --- 25 mv ai input current i in,ai ai+, ai- --- 0.1 1.0 a ai input resistance r in,ai ai+, ai- to v ag 10 --- --- m ai input capacitance c in,ai ai+, ai- --- --- 10 pf ai common mode input voltage range v cm,ai ai+, ai- 1.2 --- v dd -1.2 v ai common mode rejection ratio cmrr ti ai+, ai- --- 60 --- db ai amp gain bandwidth product gbw ti ao, r ld 10k --- 2500 --- khz ai amp dc open loop gain g ti ao, r ld 10k --- 95 --- db ai amp equivalent input noise n ti c-message weighted --- -24 --- dbrnc ao output voltage range v tg r ld =2k to v ag 0.4 --- v dd -0.4 v load resistance r ldtgro ao, ro to v ag 2 --- --- k load capacitance c ldtgao ao --- --- 100 pf load capacitance c ldtgro ro --- --- 200 pf ao & ro output current i out1 0.5 ao,ro- v dd -0.5 1.0 --- --- ma ro- output resistance r ro- ro-, 0 to 3400hz --- 1 --- ro- output offset voltage v off,ro- ro- to v ag --- --- 25 mv analog ground voltage v ag relative to v ss (no load) v dd /2-0.1 v dd /2 v dd /2+0.1 v v ag output resistance r vag within 25mv change --- 12.5 25 power supply rejection ratio (0 to 100khz to v dd , c-message. all signals referenced to v ag ) psrr transmit receive 40 40 60 60 --- --- dbc pai input offset voltage v off,pai pai --- --- 25 mv pai input current i in,pai pai --- 0.05 1.0 a pai input resistance r in,pai pai to v ag 10 --- --- m pai amp gain bandwidth product gbw pi pao- no load (@10khz) --- 1000 --- khz output offset voltage v off,po pao+ to pao- --- --- 50 mv load capacitance c ldpo pao+, pao- differentially or pao+, pao to v ag --- --- 1000 pf w681360 publication release date: september 2005 - 25 - revision a.2 v dd =2.7v to 3.6v; v ss =0v; t a =-40 c to +85 c; all analog signals referred to v ag ; parameter sym. condition min. typ. max. unit. pao output current i outpao 0.4 pao+,pao-- v dd -0.4 10.0 --- --- ma pao output resistance r pao pao+ to pao- --- 1 --- pao differential gain g pao r ld =300 , +3dbm0, 1khz, pao+ to pao- -0.2 0 +0.2 db pao differential signal to distortion c-message weighted d pao z ld =300 z ld =100nf + 20 z ld =100 (10ma limit) 45 --- --- 60 40 40 --- --- --- dbc pao power supply rejection ratio (0 to 25khz to v dd , differential out) psrr pa o 0 to 4khz 4 to 25khz 40 --- 55 40 --- --- db w681360 publication release date: september 2005 - 26 - revision a.2 10.5. d igital i/o 10.5.1. pcm codes for zero and full scale level sign bit magnitude bits + full scale 0 1111 1111 1111 + one step 0 0000 0000 0001 zero 0 0000 0000 0000 - one step 1 1111 1111 1111 - full scale 1 0000 0000 0000 10.5.2. pcm codes for 1khz digital milliwatt phase sign bit magnitude bits / 8 0 0100 0011 1100 3 / 8 0 1010 0011 1001 5 / 8 0 1010 0011 1001 7 / 8 0 0100 0011 1100 9 / 8 1 1011 1100 0100 11 / 8 1 0101 1100 0111 13 / 8 1 0101 1100 0111 15 / 8 1 1011 1100 0100 w681360 publication release date: september 2005 - 27 - revision a.2 11. typical application circuit 1.0 uf 1.0 uf 100pf power control 0.1 uf 8 khz frame sy nc 22 uf pcm in vdd 3.9k + 62k 2.048 mhz bit clock 1.5k 100pf 27k microphone 0.1 uf 27k 3.9k 1k electret 27k 0.01 uf 62k 1.5k u2 w681360 6 15 10 16 14 12 13 11 8 9 7 17 18 19 20 1 2 5 3 4 vdd vss pui hb fst bclkt pcmt mc lk pcmr bclkr fsr ao ai- ai+ vag vref ro- pao+ pai pao- speaker pcm out hp filter select figure 11.1: typical handset interface w681360 publication release date: september 2005 - 28 - revision a.2 12. package drawi ng and dimensions 12.1. 20l sog (sop)-300 mil small outline package (same as sog & soic) dimensions l o c e h a a e b d seating y 0.2 gauge e 1 20 11 10 dimension (mm) dimension (inch) symbol min. max. min. max. a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 e 7.40 7.60 0.291 0.299 d 12.60 13.00 0.496 0.512 e 1.27 bsc 0.050 bsc h e 10.00 10.65 0.394 0.419 y - 0.10 - 0.004 l 0.40 1.27 0.016 0.050 0 0o 8o 0o 8o w681360 publication release date: september 2005 - 29 - revision a.2 12.2. 20l ssop-209 mil shrink small outline package dimensions 1 20 d e e y b a a a seating plane dteail l l detail seating plane e h 10 11 b dimension (mm) dimension (inch) symbol min. nom. max. min. nom. max. a - - 2.00 - - 0.079 a1 0.05 - - 0.002 - - a2 1.65 1.75 1.85 0.065 0.069 - b 0.22 - 0.38 0.009 - 0.015 c 0.09 - 0.25 0.004 - 0.010 d 6.90 7.20 7.50 0.272 0.283 0.295 e 5.00 5.30 5.60 0.197 0.209 0.220 h e 7.40 7.80 8.20 0.291 0.307 0.323 e - 0.65 - - 0.0256 - l 0.55 0.75 0.95 0.021 0.030 0.037 l1 - 1.25 - - 0.050 - y - - 0.10 - - 0.004 0 0o - 8o 0 - 8o w681360 publication release date: september 2005 - 30 - revision a.2 12.3. 20l tssop - 4.4x6.5 mm plastic thin shrink small outline package (tssop) dimensions dimension (mm) dimension (inch) symbol min. nom. max. min. nom. max. a - - 1.20 - - 0.047 a1 0.05 - 0.15 0.002 - 0.006 a2 0.80 0.90 1.05 0.031 0.035 0.041 e 4.30 4.40 4.50 0.169 0.173 0.177 he 6.40 bsc .252 bsc d 6.40 6.50 6.60 0.252 0.256 0.260 l 0.50 0.60 0.75 0.020 0.024 0.030 l1 1.00 ref 0.039 ref b 0.19 - 0.30 0.007 - 0.012 e 0.65 bsc 0.026 bsc c 0.09 - 0.20 0.004 - 0.008 0 0o - 8o 0o - 8o y 0.10 basic 0.004 basic w681360 publication release date: september 2005 - 31 - revision a.2 12.3. qfn-32l quad flat pack no leads package (qfn) dimensions l w681360 publication release date: september 2005 - 32 - revision a.2 13. ordering information winbond part number description product family w681360_ _ w681360 package material: blank = standard package g = pb-free (rohs) package package type: s = 20-lead plastic small outline package (sog/sop) r = 20-lead plastic shrink small outline package (ssop) w = 20-lead plastic thin shrink small outline package (tssop) y = 32-quad flat no leads package (qfn) when ordering w681360 series devices, please refer to the following part numbers. part number W681360S w681360r w681360w W681360Sg w681360rg w681360wg w681360yg* * w681360yg available in pb-free (rohs) package only w681360 publication release date: september 2005 - 33 - revision a.2 14. version history version date page description a.1 april 2004 all preliminary specification a.15 april 2005 32 add important note a.16 september, 2005 2 6, 7 9 10, 12 22 27 31 32 added reference to pb-free rohs packaging and to v rms added reference to qfn-32l package added qfn-32l pinout added pin numbers to tables capitalized logic high/low added reference to v rms improved application diagram added qfn-32l mechanical dimensions added y and g package ordering code w681360 publication release date: september 2005 - 34 - revision a.2 important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical im plantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. the information contained in this da tasheet may be subject to change without notice. it is the responsibil ity of the customer to check the winbond usa website ( www.winbond-usa.com ) periodically for the latest version of this document, and an y errata sheets that ma y be g enerated |
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